Is there a way to monitor memory bandwidth utilisation?
Is there a way to monitor memory bandwidth utilisation?
KDE System Monitor and the like have easy ways of monitoring how many bits per second are going in and out of your storage at a given time, is there anything similar for memory?
Non-ECC memory controllers don't really track the flow of information in and out, the same way your CPU can't track that as well until it hits a register. CPU and Memory use clock speed regulated by voltage to pass data back and forth with no gates between, so there isn't a way to directly monitor and get feedback about the flow of information until it hits a destination that does report back or gatekeep for whatever it is (performance registers for example).
You can view the frequency of your running memory, which should give you an idea of the speed at which things will pass in/out, but that's about all you're going to get unless you find a utility that pulls a bunch of information from /proc and consolidates it all, but even then I believe you'd only be seeing an approximation and not live feedback about what's passing through memory.
could you please explain what you mean by no gates?
I guess, but not simply. Probably easier to look it up, but I'll take a stab at it:
The CPU is informed how much memory is available to use, and the address spaces across the memory provisioned when it is assigned work, so it "decides" what it's supposed to work with by using its own logic gates.
The memory controller has a logic system of its own that decides how read/write work happens when it's assigned work.
Between the two there are no gates that measure how much traffic is flowing between them. This is just a bus that passes signals back and forth (caching gets more complex so I'll skip that).
So the signals passed back and forth between these two pieces of hardware doesn't have a place where it can measure exactly what is passed back and forth, it just exists to provide a pathway to allow the signals.
ECC memory passes parity bits with its payload, sort of like a TCP conversation, so it's controller knows what is passed to it and if the expected payload is intact. Because this exists on the memory controller, you can read those values and find out what is passing through it to measure what OP is sort of asking about (though it's so fast it wouldn't make sense without sanitizing the data into a normalized measure somehow).
CPUs count cache data movements. Each L3 cache miss is a memory load.